The PSoC Core
The PSoC Core is a powerful engine that supports a rich instruction set. It encompasses SRAM for data storage, an interrupt controller, sleep and watchdog timers, IMO (Internal Main Oscillator), and ILO (Internal Low speed Oscillator). The CPU core, called the M8C, is a powerful processor with speeds up to 12 MHz. The M8C is a two MIPS, 8-bit Harvard architec-ture microprocessor.
System Resources provide additional capability such as a con-figurable I2C slave or SPI master-slave communication inter-face and various system resets supported by the M8C.
The Analog System is composed of the CapSense PSoC block and an internal 1.8V analog reference. Together they support capacitive sensing of up to 28 inputs.
The CapSense Analog System
The Analog System contains the capacitive sensing hardware. Several hardware algorithms are supported. This hardware per-forms capacitive sensing and scanning without requiring exter-nal components. Capacitive sensing is configurable on each GPIO pin. Scanning of enabled CapSense pins is completed quickly and easily across multiple ports.